TD03
-----------------------------exercice1: décodeur2/4-------------------------
--------------------------affectation sélective
library ieee;
use ieee.std_logic_1164.all;

ENTITY EXO_2B IS
PORT(
d : IN STD_LOGIC_VECTOR (1 downto 0);
y : OUT STD_LOGIC_VECTOR (3 downto 0));
END EXO_2B;

ARCHITECTURE decoder2_4 OF EXO_2B IS
BEGIN
WITH d SELECT
y <= "0001" WHEN "00",
     "0010" WHEN "01",
     "0100" WHEN "10",
     "1000" WHEN "11",
     "0000" WHEN others;-- si on met pas when others une erreur sera produite à cause la non utyilisation 9 des valeurs métalogiques, sauf que si on déclare d bit_vector
END decoder2_4;
-------------------------affectation conditionnelle
library ieee;
use ieee.std_logic_1164.all;

ENTITY EXO_2C IS
PORT(
d : IN INTEGER RANGE 0 to 3;-- c'est une autre idée de déclarer d, mais tjs valable de le mettre comme vecteur
y : OUT STD_LOGIC_VECTOR (0 to 3));
END EXO_2C;

ARCHITECTURE decodeur2_4 OF EXO_2C IS
BEGIN
y <= "0001" WHEN d=0 ELSE
     "0010" WHEN d=1 ELSE
     "0100" WHEN d=2 ELSE
     "1000" WHEN d=3 ELSE
     "0000";-- si on met pas "0000", dans ce cas pour les 9 valeurs métalogiques ça sera le x
END decodeur2_4;

-----------------------------exercice2--------------------------------------
-----------------------------affectation selective
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity EXO_3 is
    Port ( a : in  STD_LOGIC_VECTOR (3 downto 0);
           s : in  STD_LOGIC_VECTOR (1 downto 0);
           y : out  STD_LOGIC);
end EXO_3;

architecture selective of EXO_3 is
begin
with s select
y <=a(0) when "00",
    a(1) when "01",
	a(2) when "10",
	a(3) when "11",
	'0' when others;
end selective;
-----------------------------affectation conditionel
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity EXO_3C is
    Port ( a : in  STD_LOGIC_VECTOR (3 downto 0);
           s : in  STD_LOGIC_VECTOR (1 downto 0);
           y : out  STD_LOGIC);
end EXO_3C;

architecture condition of EXO_3C is
begin
y <=a(0) when s="00" else
    a(1) when s="01" else
	a(2) when s="10" else
	a(3) when s="11" else
	 '0';
end condition;
-----------------------------exercice3: BCD-7segment----------------------
library ieee;
use ieee.std_logic_1164.all;

ENTITY EXO_4 IS
PORT( d3, d2, d1, d0 : IN std_logic;
a, b, c, d, e, f, g : OUT std_logic);
END EXO_4;

ARCHITECTURE BCD_7_segments OF EXO_4 IS
SIGNAL input : std_logic_VECTOR (3 downto 0);-- on peut définir input comme vecteur d'entrée dans l'entée et on ingnore cette ligne sauf que on veut montrer l'utilisation de l'opérateur &
SIGNAL output: std_logic_VECTOR (6 DOWNTO 0);-- même ici on peut décalrer output dans l'entité, mais seulement on a travaillé avec a,b,c,d,e,f,g pour montrer les ségements de l'afficheur
BEGIN
process
begin
input <= d3 & d2 & d1 & d0;
case input is
WHEN "0000" => output <= "1111110";
WHEN "0001" => output <= "0110000";
WHEN "0010" => output <= "1101101";
WHEN "0011" => output <= "1111001";
WHEN "0100" => output <= "0110011";
WHEN "0101" => output <= "1011011";
WHEN "0110" => output <= "0011111";
WHEN "0111" => output <= "1110000";
WHEN "1000" => output <= "1111111";
WHEN "1001" => output <= "1110011";
WHEN others => output <= "1111111";--les autres combinaisons sont des états indéterminés forcés à 1 selon le datacheets définition des sorties
end case;
a <= output(6);
b <= output(5);
c <= output(4);
d <= output(3);
e <= output(2);
f <= output(1);
g <= output(0);
end process;
end BCD_7_segments;
------------------------------------Exercice4------------------------------
------------------------------------if then elsif
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity EXO_5 is
    Port ( a : in  STD_LOGIC_VECTOR (3 downto 0);
           b : out  STD_LOGIC_VECTOR (3 downto 0));
end EXO_5;

architecture Behavioral of EXO_5 is
begin
process
begin
if a="0000" then 
b<="0000";
elsif a="0001" then 
b<="0001";
elsif a="0010" then 
b<="0010";
elsif a="0011" then 
b<="0011";
elsif a="0100" then 
b<="0100";
elsif a="0101" then 
b<="0101";
elsif a="0110" then 
b<="1100";
elsif a="0111" then 
b<="1101";
elsif a="1000" then 
b<="1110";
else b<="XXXX";
end if;
end process;
end Behavioral;
---------------------exercice5----------------------
library ieee;
use ieee.std_logic_1164.all;

entity EXO_1 is
port (ADDR : in natural range 0 to 15;--c'est l'entrée du décodeur 4 bits
      MEM_0to3, MEM_8to11, MEM_12to15 : out std_logic_vector (3 downto 0);
      MEM_4to7 : out std_logic_vector(3 downto 0));
end EXO_1;

architecture dec_adr of EXO_1 is
begin
process (ADDR)-- process pour un systeme combinatoire
begin
-- initialisations il s'agit de mettre toutes les sorties du déccodeur à zéro
MEM_0to3 <= "0000"; MEM_8to11 <= "0000"; MEM_12to15 <= "0000"; MEM_4to7 <= (others =>'0');
-- décodage
Case ADDR is
when 0 to 3 => MEM_0to3 <= "1111";
when 4 => MEM_4to7(0) <= '1';
when 5 => MEM_4to7(1) <= '1';
when 6 => MEM_4to7(2) <= '1';
when 7 => MEM_4to7(3) <= '1';
when 8 to 11 => MEM_8to11 <= "1111";
when 12 to 15 => MEM_12to15 <= "1111";
End case ;
end process;
end dec_adr;
--------------------exercice6----------------------
----------On a utilisé un package----------------------------------
package alu_pkg is
type alu_op is (ADD, SUB, INC1, DEC1, LNOT, LAND, LOR, LSHl) ; -- compile séparément dans une autre fenêtre
end alu_pkg;
-------------------------------------------------------------
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;-- on peut considéré signé dans ce cas: useIEEE.std_logic_signed.all
use IEEE.numeric_bit.all
use work.alu_pkg.all;

entity EXO_2 is
port (OP: in alu_op;
         A, B: IN STD_LOGIC_VECTOR(7 DOWNTO 0); --on considère des opérandes de 8 bits;
         q: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
end entity EXO_2;

architecture dfl of EXO_2 is
begin
process
with OP select
Q <= A + B when ADD,
     A - B when SUB,
     A + 1 when INC1,
     A - 1 when DEC1,
     not A when LNOT,
   A and B when LAND,
    A or B when LOR,
   A srl 1 when LSHl;
End process;
end dfl;
---------------------exercice7----------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;--ieee.std_logic.arith.all;
use ieee.numeric_std.all;
entity EXO_3 is
port (Sel : in std_logic_vector(4 downto 0); -- sélecteur de l’opération
       CI : in std_logic; -- retenue d’entrée
     A, B : in std_logic_vector (7 downto 0); -- opérandes
        Y : out std_logic_vector (7 downto 0)); -- résultat
end entity EXO_3;

architecture fct of EXO_3 is
signal LO, AO, NSO : std_logic_vector (7 downto 0);
signal SEL3 : std_logic_vector(2 downto 0);
begin
-- unité logique--
with SEL(1 downto 0) select
LO <= A and B when "00",
       A or B when "10",
      A xor B when "10",
        not A when "11",
(others=>'0') when others;

-- unité arithmétique--
SEL3 <= SEL(1 downto 0) & CI;
with SEL3 select
AO <= A when "000",
      A + 1 when "001",
      A + B when "010",
  A + B + 1 when "011",
  A + not B when "100",
      A - B when "101",
      A - 1 when "110",
          B when "111";
(others=>'0') when others;

-- multiplexeur--
NSO <= LO when SEL(2) = '1' else AO;

-- unité de décalage--
with SEL(4 downto 3) select
Y <= NSO when "00",
     NSO sll 1 when "01",
     NSO srl 1 when "10",
    (others => '0') when others;
end architecture fct;