TD02
-----------------------------exercice1--------------------------------------
---------------------Architecture flot_data
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity EXO_1 is
    Port ( a : in  bit;
           b : in  bit;
           y : out  bit);
end EXO_1;

architecture flot_data of EXO_1 is
begin
y <= (a and not(b)) or (b and not(a));
end flot_data;

-----------------------------exercice2: décodeur2/4-------------------------
---------------------affectation concurrentielle
library ieee;
use ieee.std_logic_1164.all;

ENTITY EXO_2 IS
PORT(d1, d0 : IN bit;--on peut aussi définir les entrées et les sorties comme veteur
y0, y1, y2, y3 : OUT bit);
END EXO_2;

ARCHITECTURE decoder2_4 OF EXO_2 IS
BEGIN
y0 <= (not d1) and (not d0);
y1 <= (not d1) and (d0);
y2 <= (d1) and (not d0);
y3 <= (d1) and (d0);
END decoder2_4;
-----------------------------exercice3--------------------------------------
-----------------------------affectation concurrente
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity EXO_3B is
    Port ( D0,D1,D2,D3 : in bit;
           B,A : in bit_vector (1 downto 0);
           y : out  bit);
end EXO_3B;

architecture flot_data of EXO_3B is
begin
y <= (not(A) and not(B) and D0) or
     (not(A) and B and D1) or
	 (A and not(B) and D2) or
	 (A and B and D3);
end flot_data;
------------------------------------Exercice4------------------------------
------------------------------------Concurentielle
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity EXO_5B is
    Port ( A,B,C,D : in  STD_LOGIC;
           E,F,G,H : out  STD_LOGIC;
end EXO_5B;

architecture Behavioral of EXO_5B is
begin
E <= (not (A) and B and not (C) and D) OR (not (A) and B and C and not (D))OR (not A and B and C and D) OR(A and not(B) and not(C) and (D)) OR (A and not B and not C and D)
F <= .....................
G <= .....................-- les équations boulienne se trouve dant le TD01
H <= .....................
end Behavioral;